Lock-in Testing

For use with Thermalyze Thermal Image Analysis Software

PN0172

Lock-in thermography (LIT) is a process of automatically and repeatedly powering an electronic device at regular intervals while thermal images of the device are analyzed by software. The following description is over simplified, but helps to provide a basic understanding of the Lock-in Thermography process.

Over many power cycles, thermal images captured while the device is powered are added together. Likewise, thermal images capture while the device is unpowered are added together. The unpowered sum is subtracted from the powered sum resulting in an Lock-in image that represents temperature differences between the powered and unpowered state. As the LIT test continues, more and more thermal images are added together, resulting in a Lock-in image with higher and higher sensitivity. In fact, test sensitivity is inversely proportional to the square root of the number of images captured during a lock-in test. Typically, a lock-in test is allowed to run until the fail site is detected and can be precisely located. In many cases, a temperature increase less than 1 mK (0.001°C) and power dissipation below 10 microW can often be detected.

Device power can be applied at a Cycle Frequency of up to 15 Hz. Performing LIT tests at lower frequencies improves test signal/noise due to higher device heatup. Higher frequency tests improve hot spot spatial resolution by reducing thermal diffusion into adjacent areas of the device.

Applications

Lock-in thermography tests are used to detect and locate the following faults:

Thermography
- Leakage current and resistive short circuits on semiconductor devices, wafers, SMD components, bare circuit boards and flex circuits
- Power-to-ground short circuits on populated circuit boards
Photon Emission

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Overview

Specifications

Setup

Operation

Troubleshoot

Maintenance

Overview

Figure 1: Lens resolution comparison at 5µm, 20µm, and 80µm.

Overview Instrument Control Relay Control Test Images Defect Depth Frequently Asked Questions

Overview

Steady-state thermography is limited to detecting hot spots that heat up a minimum of 100 mK (0.100°C). This may be useful for locating shorts on high-power devices but is inadequate for detecting low power defects such as semiconductor device leakage current or short circuit with very low or very high resistance. Steady-state thermography also suffers from poor spatial resolution as the heat from localized hot spots diffuses rapidly, blurring the location of the heat source.

Lock-in thermography is a process of automatically and repeatedly applying voltage to a device at regular intervals using a laboratory voltage source while the temperature response of the device is integrated and analyzed over time. Over many power cycles, the sum of thermal images captured while the device is unpowered are subtracted from the sum of thermal images captured while the device is powered. Using this technique, hot spots that heat up less than 1mK (0.001°C) and dissipate below 100 µW can be detected. Increasing the number of test cycles results in improved test sensitivity and weak sources of heat arising during normal operation of the device can even be detected.

The frequency at which voltage is cycled can be set from below 1 Hz up to 15 Hz. Performing lock-in tests at lower frequencies improves test signal/noise due to higher device heating. Higher frequency tests improve hot spot spatial resolution by reducing thermal diffusion into adjacent areas of the device.

Instrument Control

Lock-in thermography is a process of automatically and repeatedly applying voltage to a device at regular intervals using a laboratory voltage source while the temperature response of the device is integrated and analyzed over time. The Instrument Setup window within Thermalyze is used to setup and control a Keithley voltage source (such as a source measure unit) via USB interface.

Voltage can be cycled between zero volts and a higher voltage, or between two non-zero voltages. Current flow and applied voltage are read from the instrument and displayed at the bottom of the window. To help operators determine appropriate test voltage, current limit and test time, fail site power dissipation and resistance are calculated and displayed.

Thermalyze Software: See Thermalyze Operation documentation for Instrument Control software features and operation.

Supported Instrument Models

See Thermalyze documentation for a list of supported instrument models.

IV Curve Plotting

Plot the device current response to an applied voltage range.

Supported Instrument Models

Keithley graphical SMU (source measure unit) models 2450, 2460, 2461, and 2470

Keithley series standard 2400 source measure units (requires National Instruments USB GPIB controller model GPIB-USB-HS+)

Keithley series 2280 DC power supplies

Relay Control

Lock-in thermography is a process of automatically and repeatedly applying voltage to a device at regular intervals using a laboratory voltage source while the temperature response of the device is integrated and analyzed over time. High frequency (up to 15 Hz) or high current (up to 6 Amp) mechanical relays can be used to control voltage from your existing source meter or power supply. Relay outputs can also be used to trigger external test equipment when more sophisticated device voltage control is required. Mechanical relays have zero leakage current in the off state which is advantages when performing lock-in tests on devices with low leakage current.

Test Images

Single Phase Image

A single phase image displays temperature increases at a specific time in the cycle. The time within the cycle is expressed using phase angle with 0 degrees representing the beginning of the cycle when voltage is applied and -180 degrees representing when voltage is removed. A phase angle of -360 degrees represents the end of the cycle and is equivalent to a phase angle of 0 degrees.

Single phase images are used to locate faults in the xy direction. They can also identify areas that heat up at different times within the cycle providing a correlation with defect depth. Single phase images typically produce the highest xy spatial resolution of all Lock-in images.

Amplitude Image

An amplitude image displays all temperature increases at any time during the cycle and is commonly used to determine fault location in the xy direction.

Phase Angle Image

The phase image displays the phase angle of heating at each point in the image. Phase angle is most often associated with defect depth because heating phase angle represents the time within a cycle when internally generated heat reaches the surface. Phase angle represents the delay between powering a device and the resulting surface heating. When analyzing packaged devices and stacked die, phase angle is used to estimate the depth of a defect.

Phase angle is measured in units of degrees and has a range of 0 to -360 degrees. A phase angle of 0 degrees indicates device heating occurring immediately after power is applied and takes place at or near the surface. Negative phase angle values, such as -120 degrees, indicate device heating occurring at some time after power is applied and somewhat below the surface. Larger negative values of phase angle indicate heating occurring at even greater depths.

Thermal Overlay

A thermal overlay is a grayscale thermal image of the device produced by averaging all of the captured images that have been accepted in the lock-in test. When thousands of images have been accepted, the thermal overlay image noise is significantly reduced providing a high resolution image that can be merged with the single phase, amplitude, and phase angle images to facilitate locating fault xy coordinates.

Cycle Images

A cycle image displays device heating at a specific time during a cycle. Cycle images are useful for visualizing heat propagation across a device during the cycle.

Defect Depth

Determining fault depth in 3-dimensional system-in-package (3D SiP) devices is becoming increasingly important due to their expanding complexity and decreasing dimensions. As the number of stacked die in 3D SiP devices grows, isolating the root cause of defects within the package becomes more challenging. Sentris provides a non-destructive technique to localize the depth of faults through 3D SiP packages.

Phase Angle

Phase angle represents the time delay between powering a device and subsequent heating on its surface and can be used to estimate fault depth. The magnitude of time delay, or phase angle, is dependent on defect depth but also on the thermal conductance of materials within the device.

Applying Voltage

Many 3D SiP devices undergo an initialization process that is triggered at a specific voltage level. If the applied voltage is cycled between 0 and a value above the initialization voltage level, the initialization process may cause non-defect related power dissipation that can interfere with detecting the true fail site. In these cases, the device should be initialized before the lock-in test begins, and the applied voltage should be cycled between two voltages that are above the initialization voltage.

Additionally, some 3D SiP devices include on-chip voltage regulators and defect power dissipation may not correlate with on-off power cycling. In these cases, device test equipment may need to be synchronized with the lock-in cycles in order to activate fail sites.

Calculating Defect Depth - Method 1

3D SiP devices are complex structures comprised of multiple stacked semiconductor die, die-attach adhesive, and package mold compound. Modelling the thermal diffusion and phase relationships of heat originating from defect sites using thermal simulation software can be very difficult.

Sentris provides a simple method to describe the internal structure of a device by entering the thickness and thermal conductivity of each material layer. Phase angle data from testing the device on both the top and bottom sides is then entered to calculate defect depth.

Calculating Defect Depth - Method 2

The thermal properties of die, adhesive, and mold compound are often not known precisely and the interfaces between these materials makes the problem even more complex. In these cases, it may be more effective to estimate fault depth by correlating phase angle with the depth of known internal faults.

By measuring the phase angle of faults at known depths, a relationship between phase angle and depth can be plotted. This plot can then be used to estimate the depth of unknown faults by comparing their phase angle to the plot. This method requires phase angle results from only one side (top or bottom) of a device.

The relationship between phase angle and depth is dependent on both test frequency and fault power dissipation. For this reason, the power dissipated in the defect must remain consistent when performing all tests on a specific device. A suitable frequency should be selected that results in a high plot slope but also covers all potential fault depths. This will enable differentiation between different die levels more clearly. Standard procedure is to begin testing at 1 Hz and depending on the phase results of the test, raise or lower test frequency accordingly.

Calculating Defect Depth - Method 3

This method is similar to method 2, however instead of measuring the phase angle of faults at known depths, internal reference heat sources are used. Internal I/O diodes located on multiple die levels are typically used as reference heat sources by forward biasing them. To create a defect depth plot, the device must be tested by cycling power to at least two reference heat source whose depths are known.

Frequently Asked Questions

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Specifications

Leakage Current

Semiconductor device leakage current is a quantum phenomenon where mobile charge carriers (electrons or holes) tunnel through an insulating region. Leakage current occurs primarily inside transistors, but leakage can also occur between interconnects. It results in increased power consumption and if sufficiently large, can cause complete circuit failure. Leakage current is often very difficult to detect due to the small amount of heat generated and the large number of components on a chip. Because of its high temperature detection sensitivity, lock-in thermography is an effective tool to detect and pinpoint leakage current.

Low Resistance Shorts

Low resistance shorts often provide a path that drains the majority of current on electronic circuit, starving other components of current, preventing them from operating properly and generating significant heat. For this reason, the majority or heating occurs at the site of a low resistance short when voltage is applied to a circuit, enabling these shorts to be easily detected and located using lock-in thermography.

High Resistance Shorts

Depending on the specific design of a circuit, high resistance shorts may not sink enough current to prevent other components from operating and generating significant heat. It may be difficult to isolate the short as the heat generated in other components masks the fault site heating. During a lock-in thermography test, localized heating occurring at different times during the lock-in test cycle is displayed and evaluated to determine the site of the fault. When testing silicon devices, applied voltage should be limited to 0.5V to avoid activating and heating up silicon devices.

Test Sensitivity

Increasing the number of lock-in test cycles results in improved test sensitivity. Test sensitivity is proportional to the square root of the number of thermal images captured during the test. Using this technique, hot spots that heat up less than 1mK (0.001°C) and dissipate below 10 µW can be detected. Weak sources of heat arising during normal operation of the device can also be detected.

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Setup

The topics in this section include a step-by-step guide to setting up and performing a lock-in thermography test by applying voltage to the thermal test chip diode using a DC current limiting power source. If you did not purchase the thermal test chip, you can use any device with a known resistive short or leakage.

Voltage Source Setup

Procedure

Set the power source output to 1 Volt and current limit to 1mA, but do not arm the output yet.

Test Tip: When testing a device with a resistive short or leakage, set the voltage output to a very low value initially (such as 1mV) to prevent damage to the device or relay. Open the Relay Setup window (see Figure 1) and use the test boxes on the right side of the window to momentarily close a relay to read current draw on the voltage source. Increase voltage until the power dissipated in the device (P = I x V) is approximately 200µW.

Figure 1: Relay setup window

Software Settings

Procedure

Confirm that the Image Averaging button is set to (see Figure 2).
Press the Capture Images button (see Figure 2) to start capturing images.
Click the Auto Scale Palette button (see Figure 2) to automatically scale the color palette.
Focus the lens on the test chip.

Caution: Do not lower camera so that lens touches test chip.

Figure 2: Thermalyze main image

Lock-in Test Setup

Procedure

Press the button (see Figure 3 upper right) to open the Lock-in Thermography window.
Confirm that the Image Size button (see Figure 3 upper center) is unpressed so that the Lock-in Thermography window is small.
Confirm that the Auto Scale Each box (see Figure 3 upper right) is checked.
Press the Relay Setup button (see Figure 3 upper left) to open the Relay Setup window. When the Select Relay Device window opens, click OK.
In the Relay Setup window, make sure the Relay Device Type selected is “PCIe-AC5” (see Figure 4), and then press the Initialize Selected Device button.
Confirm that the Enable Relays and Relay #5 boxes are checked.
Close the Relay Setup window.
In the Lock-in Thermography window, press the Advanced Settings button (see Figure 3 upper left) to open the Advanced Settings window.
Confirm that the Auto Rejection Enable box (see Figure 6) is checked and then move the window to the lower right of the screen.
In the Lock-in Thermography window, Press the Overlay Palette Scale button (see Figure 3 lower center) and then move the Thermal Overlay Palette window to the lower left of the screen.
Arm the power supply output.

Figure 3: Lock-in Thermography window

Start a Test

Procedure

In the Lock-in Thermography window, click the Clear Test button (see Figure 3 lower left) to delete any existing test data.
Confirm that the Overlay Show box (see Figure 3 lower center) is unchecked.
Confirm that “Single Phase” is selected as the Update option (see Figure 3 lower center).
Confirm that the Phase Angle slider (see Figure 3 lower center) is set to 0°.
To start the LIT test, press the Testing On/Off button (see Figure 3 lower left).
While the test is running, check the Advanced Settings window for red flashing of Image Rejection Parameters (see Figure 6). If flashing occurs more regularly than once per 10 seconds, raise the Auto Rejection Safety Factor (see Figure 6) until no fields flash red.
When a clearly defined hot spot can be distinguished in the lock-in image, press the Testing On/Off button (see Figure 3 lower left) again to stop the test.

Display Test Results

Procedure

In the Lock-in Thermography window, check the Overlay Show box (see Figure 3 lower center) to display the grayscale thermal overlay.
Drag the Overlay Range slider (see Figure 3 lower center) to set the proportion of overlay displayed with the hot spot.
On the Thermal Overlay Palette window, click the Auto button (see Figure 5) to automatically adjust the thermal overlay palette.
In the Lock-in Thermography window, press the Image Size button (see Figure 3 upper center) to display a large lock-in image.
Use the Zoom buttons and Pan button (see Figure 3 upper center) to zoom in and pan the lock-in image.

Figure 4: Relay setup window

Figure 5: Thermal overlay palette window

Figure 6: Advanced setting window

Defect Location

Procedure

In the Lock-in Thermography window, click the Delete Region button (see Figure 3 lower right) to delete an existing region.
In the Lock-in Thermography window, press the Point Region button (see Figure 3 lower right) and then click on a feature in the lock-in image (such as a corner or bond pad) to place a reference region.
Press the Measure Distance button (see Figure 3 lower right) and then move the Measure Distance window next to the hot spot.
Click on the center of the hot spot to display the x, y, and straight-line distance (in microns) from the reference region to the hot spot in the Measure Distance window.

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Operation

Thermalyze Operation > Lock-in Thermography

Test Tip: For a lock-in thermography test to be performed properly, the camera and device must not move during the test.

Lock-in Test Tips

Lens Selection

Description

When selecting a specific lens for a lock-in test pixel resolution, field-of-view, and working distance are fundamental lens characteristics to consider. Sensitivity is also an important factor as it determines if very low levels of heating can be detected and if so, the length of test time required.

Working f/# is a lens specification that indicates light gathering capability and measurement sensitivity. Lower f/# values result in more light and higher sensitivity. The working f/# of the 20µm, 80µm, and Macro lenses are all close to 1.0 and therefore have similar sensitivity. The 40µm lens is specially designed with f/# of 0.76 for optimal sensitivity. Sensitivity is proportional to the inverse of f/# squared and therefore the 40µm lens is nearly twice as sensitive as the 20µm, 80µm, and Macro lenses. Due to constraints of lens design in the LWIR at higher magnifications, the f/# of the 5µm lens is 2.6, resulting in approximately 7x less sensitivity than the 20µm, 80µm, and Macro lenses.

Lock-in Test Time

Test sensitivity increases with test time and is proportional to the square root of the number of images captured during the test. Therefore, compared with the 20µm, 80µm, and Macro lenses, tests using the 40µm lens require less than 1/3 the time to detect a given temperature rise and tests using the 5µm lens require almost 50 times as long.

Current Limit

Description

Many voltage sources provide current limiting to prevent high current levels that can alter fault characteristics or damage devices. Current limiting works by automatically reducing output voltage until current output no longer exceeds the limit.

All current limiting voltage sources require time (specified by slew rate) to reduce output voltage when limiting current. Slew rate is typically very short and is usually measured in microseconds. During this short time however, it is possible for high current to flow through a device, altering the defect or damaging the device. The slew rate of source meters is typically much faster than power supplies and therefore, the potential for damage is much less prevalent when using source meters. Current limiting should not be relied upon to protect devices and should be used only as a backup if fault resistance decreases while testing, resulting in higher current draw.

Voltage Source Setup

Description

Setting up a voltage source for a lock-in test requires the following procedure:
Set the current limit to a level appropriate for the circuit so that the potential for altering fault characteristics or damaging the device is minimized.
Set the voltage output to a very low level (such as 1 mV or lower). In the case of a dead short (very low resistance), test circuit resistance is typically a minimum of 0.1 ohm, due to connector, probe, and lead resistance. Note that when 1 mV is applied to a 0.1 ohm resistance, 10 mA will flow.
Test the voltage source settings by activating the relay or instrument output.
Note the power dissipation in the short according to actual voltage output (after current limit) and current flow. Also note the short resistance so that any change in resistance is considered when adjusting voltage source settings. If power dissipation is too low to detect, increase current is increased in small increments until adequate power dissipation is reached.

Power Dissipation

Description

Whether a resistive short can be detected is determined by the local temperature increase site when current passes through the fault. Temperature increase is directly proportional to the magnitude of power dissipated in the short. When using a DC voltage source, dissipated power is determined by multiplying current draw by the applied voltage (after any current limiting voltage reduction). Current and voltage output are typically displayed on most voltage sources. Make sure that the actual output voltage is displayed and not the set voltage.

Low Resistance Shorts

Resistance is the most important fault characteristic when determining voltage and current limit settings. Resistance also indicates if a short is detectable and if so, the time required for detection. Low resistance shorts (< 1 Ohm) can be difficult to detect because in most cases, current must be limited to avoid circuit damage. For low resistance shorts, dissipated power is calculated according to P = I x I x R and limiting current restricts the amount of power that can be dissipated in the short.

High Resistance Shorts

High resistance shorts (> 1 Mohm) can also be difficult to detect due to circuit maximum voltage limitations. For high resistance shorts, dissipated power is calculated according to P = (V * V) / R and limiting voltage restricts the amount of power that can be dissipated in the short. To detect very high resistance shorts (for example 10 Mohm), 100 V must be applied for power dissipation of 100 µW.

Device Packages

Packaged electronic devices and circuit boards require higher levels of power dissipation for fault detection than unpackaged or decapsulated devices as heat must travel through the package material to reach the surface where it can emit detectable infrared energy.

Lock-in Test Time

Test sensitivity increases with test time and is proportional to the square root of the number of images captured during the test. And because fault temperature rise is proportional to power dissipation, test time is proportional to the inverse of power dissipation squared. Detection of a 10µW fault, for example, requires 4 times as long as detection of a 20µW fault and 100 times as long as a 100µW fault.

To detect faults in less than 30 minutes on bare or decapsulated devices, 10µW minimum power dissipation is typically required. 100µW can usually be detected in less than one minute. Less than 10µW may require several hours or even overnight testing. Temperature rise of 1mK (0.001°C) can be detected within 5 minutes. If a test is run for about 10 hours, heating of 0.1mk (0.0001°C) can be detected.

Probe Tip Heating

Description

When short resistance is low (< 1 ohm) higher current must be passed through the fault to generate enough heat to detect. The needle probe contact is ~ 0.1 ohm if good contact is made and therefore some heat will be generated at the probe tip. For example, if 20 mV is applied to a 1 ohm short, 20 mA will pass through the defect generating 400 µW (P = I x V = 0.02 x 0.02). However, current passing through the probe tip will generate 40 µW (P = I x I x R = 0.02 x 0.02 x 0.1). In most cases, probe tip heating can be ignored as it is of lower magnitude than fault heating. If poor electrical contact is made at the probe tip however, heat generated at the tip may be much higher and can mask fault heating.

Making Probe Tip Contact

Setup the voltage source with appropriate voltage and current limit settings.
Check needle tip and replace if broken.
Position the probe tips so that they contact the faulty circuit.
Turn on the voltage source output.
Adjust the pressure of the probe tip while until maximum current flow is reached.

Avoid Blocking Lens

Description

The majority of infrared energy that strikes the camera detector travels from the target area through the center of the lens. Avoid obstructions that block these direct infrared rays. For example, do not place the XYZ probe positioner needle mount directly over the area to be imaged. Even though the underlying area may still be visible in the thermal image due to marginal infrared rays traveling from the target area through the periphery of the lens, significant infrared energy is blocked by the needle mount, resulting in lower measurement and test sensitivity.

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